Design of Low-latency Synthesizable PUCCH Demodulation Unit Using Simulink HDL Coder | IEEE Conference Publication | IEEE Xplore

Design of Low-latency Synthesizable PUCCH Demodulation Unit Using Simulink HDL Coder


Abstract:

Low-latency synthesizable demodulation unit for 5G-NR Physical Uplink Control Channel (PUCCH) Format 0 is designed using Simulink Hardware Description Language (HDL) Code...Show More

Abstract:

Low-latency synthesizable demodulation unit for 5G-NR Physical Uplink Control Channel (PUCCH) Format 0 is designed using Simulink Hardware Description Language (HDL) Coder. The modulated sequence of PUCCH Format 0 is generated by a sequence group number and cyclic shift value depending on many higher-layer parameters and scheduling parameters. However, high-latency of the sequence generator comes from the computation of the group number and cyclic shift value. In this paper, the efficient architecture is introduced for the sequence generator for the low-latency synthesizable demodulation unit and verified under the FPGA-in-the-loop (FIL) workflow using Simulink HDL Coder and Xilinx ZCU102 evaluation board. This approach is useful to provide validation before hardware implementation.
Date of Conference: 20-22 October 2021
Date Added to IEEE Xplore: 07 December 2021
ISBN Information:
Print on Demand(PoD) ISSN: 2162-1233
Conference Location: Jeju Island, Korea, Republic of

Funding Agency:


References

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