ILP models for energy and transient power minimization during behavioral synthesis | IEEE Conference Publication | IEEE Xplore

ILP models for energy and transient power minimization during behavioral synthesis


Abstract:

The reduction of peak power, peak power differential, average power and energy are equally important in the design of low-power battery driven portable applications. In t...Show More

Abstract:

The reduction of peak power, peak power differential, average power and energy are equally important in the design of low-power battery driven portable applications. In this paper, we introduce a parameter called "cycle power function" (CPF-DFC) that captures the above power characteristics in the context of multiple supply voltage (MV) and dynamic frequency clocking (DFC) based designs. Further, we present ILP formulations for the minimization of CPF-DFC during datapath scheduling. We conducted experiments on selected high-level synthesis benchmarks for various resource constraints. Experimental results show that significant reduction in power, energy, and energy delay product, can be obtained using the proposed method.
Date of Conference: 09-09 January 2004
Date Added to IEEE Xplore: 24 August 2004
Print ISBN:0-7695-2072-3
Conference Location: Mumbai, India

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