Partial open defects in modern Static Random Access Memory (SRAM) address decoders are one of the main causes of small delays; these are hard to detect and may result in escapes and reliability problems. In addition, Aging failures - such as Bias Temperature Instability (BTI)-may worsen the situation and accelerate the degradation (i.e. increase the delay) and cause sooner field failures. This paper investigates the impact of partial opens and BTI in SRAM address decoders first separately and thereafter in a combined manner. Simulation results show that BTI impact strongly depends on the selected worldline, transistor location and addressing scheme; and it cause up to 14.27% additional delay. In addition, they show that partial opens, which do not cause hard faults and allow memory operations to pass correctly, contribute up to 23.65% additional delay. Combining these failure mechanisms reveals that the degradation can strongly be worsened and accelerate wear-out; an additional delay of up to 31.20% can be caused. This indicates the importance of incorporating appropriate design-for-reliability/testability schemes in order to guarantee the required lifetime of the memory system.