Abstract:
This paper presents the design of discret time (DT) feed-forward (FF) 2-1 cascaded Delta-Sigma (ΔΣ) modulator used in wireless communication systems. This topology can pr...Show MoreMetadata
Abstract:
This paper presents the design of discret time (DT) feed-forward (FF) 2-1 cascaded Delta-Sigma (ΔΣ) modulator used in wireless communication systems. This topology can provide several advantages over other architectures because of its relaxed requirements on the analog building blocks, mainly on the switched capacitor (SC) integrator. The design is performed by using optimized Telescopic and Gain-boosted OTAs to implement the integrator. Using AMS 0.35µm CMOS process, transistor-level simulation results indicate that the 2-1 cascaded ΔΣ modulator achieves a SNR of 47.5dB and 42dB over bandwidths of 2MHz and 3.84MHz respectively with over-sampling ratio of 16.
Published in: 2016 11th International Design & Test Symposium (IDT)
Date of Conference: 18-20 December 2016
Date Added to IEEE Xplore: 06 February 2017
ISBN Information:
Electronic ISSN: 2162-061X