This paper introduces a topology applied to LED systems that unifies high efficiency with the avoidance of electrolytic capacitors. The main idea is to reduce the redundant power processing, making the second converter to process less energy. The capacitor is reduced by increasing the ripple at the output of the power factor correction converter and using the second converter to compensate this ripple. A 75W prototype was built and compared with a single-stage topology and with an integrated two-stage topology.