In this paper, First an analysis of the effects of transient faults using simulation-based fault injection is presented in System-on-Chip Wire (SoCWire) and then a fault-tolerant infrastructure is mentioned and results is reported. Different fault models such as dead clause, stuck then, micro-operation, crosstalk, dead process and SET (Single Event Transient) have been used to evaluate the transient faults' effects on SoCWire which is described in VHDL language. Besides, reported results in SoCWire show that about 47.67% of injected faults are latent; 41.71% of faults are recovered during simulation time and the remainders 10.61% of faults are effective that cause failure. The average of fault latency is 34. As it is illustrated later the percentage of failure is decreased in fault tolerant SoCWire.