The presented paper describes an approach of dynamic positioning of functional building blocks on Virtex (Xilinx) FPGAs. The modules can be of a variable rectangular shape. Further, the on-chip location of the area to be reconfigured can be freely chosen, so that any module can be placed anywhere within the defined dynamic region of the FPGA. Thus the utilization of the chip area can be optimized, which in turn reduces e.g. costly area and power consumption. This paper describes a runtime system and the necessary framework, which is able to manage the reconfigurable area. Further it shows how a NoC approach can be applied to shorten wire lengths for communication. This will in turn save routing resources and potentially increases clock speed.