This paper presents a coarse-grained reconfigurable architecture based on an array of processing and memory cells. Memory cells are distributed and placed close to processing cells to reduce memory bottlenecks. Processing cells are instruction set processors with enhanced performance for communication-intensive inner loops. Processor communication is performed using a self-synchronizing protocol that simplifies algorithm mapping and manages unpredictable time variations. The reconfigurable architecture is described as a scalable and parameterizable SystemC transaction level model, which allows rapid architectural exploration. Our exploration environment SCENIC is used to setup scenarios, control the simulation models and to extract performance data during simulation. A case study demonstrates different implementations of a filter algorithm, and how exploration is used to tune and optimize for execution time, latency, or used resources.