Loading [a11y]/accessibility-menu.js
Soft error immune latch design for 20 nm bulk CMOS | IEEE Conference Publication | IEEE Xplore

Soft error immune latch design for 20 nm bulk CMOS


Abstract:

This paper discusses soft error immune latch (SEILA) design aiming to prevent soft errors originating from charge collection to multiple nodes. We first designed 28 nm SE...Show More

Abstract:

This paper discusses soft error immune latch (SEILA) design aiming to prevent soft errors originating from charge collection to multiple nodes. We first designed 28 nm SEILA with double height cell (DHC) and evaluated its SEU rate through neutron irradiation test. The SEU rate is at the same level with 65 nm DHC-SEILA. Next, for enhancing the soft error mitigation efficiency, we designed SEILA with triple height cell (THC) in 20 nm. The 20 nm THC-SEILA achieves 14 times lower SEU rate than 28 nm DHC-SEILA. The area overhead compared to a normal latch is 140 % in the 20 nm THC-SEILA.
Date of Conference: 19-23 April 2015
Date Added to IEEE Xplore: 01 June 2015
Electronic ISBN:978-1-4673-7362-3

ISSN Information:

Conference Location: Monterey, CA, USA

References

References is not available for this document.