Abstract:
Modeling of the threshold voltage instabilities in SiC power MOSFETs is difficult due to the fast recovery of ΔVth after positive and negative gate bias stress. This work...Show MoreMetadata
Abstract:
Modeling of the threshold voltage instabilities in SiC power MOSFETs is difficult due to the fast recovery of ΔVth after positive and negative gate bias stress. This work investigates the capture- and emission-time constants of positive and negative charge trapped in the gate oxide and at the interface as a function of gate bias and temperature. We present a measurement technique which enables time-resolved measurements of the real Vth during application-relevant bipolar AC high temperature gate stress (HTGS). We use capture and emission time (CET) maps to model the temperature and voltage dependence of the ΔVth after positive as well as negative gate stress. In addition, we provide a complete modeling approach for the ΔVth after long-term AC stress considering the full stress-history. Furthermore, we present a very accurate model for the short-term hysteresis during a bipolar AC period and we show that the threshold voltage hysteresis has no harmful effect on switching operation in real applications.
Date of Conference: 11-15 March 2018
Date Added to IEEE Xplore: 03 May 2018
ISBN Information:
Electronic ISSN: 1938-1891