The generation of new traps during TDDB may significantly accelerate BTI, since these traps are close to the dielectric-Si interface in scaled technology. This work confirms the correlation with 28nm measurement data. Based on stochastic trapping/detrapping mechanism, new compact BTI models are developed and verified with 14nm FinFET and 28nm HKMG data. The contributions of this work include: (1) Derivation of BTI models with added TDDB impact, (2) Providing test results for calibration of model parameters, and (3) Presenting device models and simulation results for circuits. At circuit level, incorporating these models illustrates a significant increase in failure rate due to accelerated BTI.