This paper investigates the effect of dummy ball on the board level reliability (BLR) by performing thermal cycling (TC) test for 5 wafer level package (WLP) products, each having two or three different dummy ball configurations. Regardless of the die thickness, the ball size and the package size, the single dummy ball array at the chip corner boosted the BLR TC performance by 30~40% and the double dummy ball array by 92%. To maximize the dummy ball effect, the dummy ball array in the chip corners should be symmetric and co-optimized with die and package size.