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Design Techniques Evaluation to Mitigate RTS Noise Effect in Column ADC of 3D Stacked Image Sensors | IEEE Conference Publication | IEEE Xplore

Design Techniques Evaluation to Mitigate RTS Noise Effect in Column ADC of 3D Stacked Image Sensors


Abstract:

ADC circuits may cause RTS column signatures in 3D stacked CMOS image sensors. This work proposes a statistical and design evaluation of RTS for 40nm node devices, used i...Show More

Abstract:

ADC circuits may cause RTS column signatures in 3D stacked CMOS image sensors. This work proposes a statistical and design evaluation of RTS for 40nm node devices, used in ADC circuits. A transistor array mimicking 3T CIS pixel array architecture is used for RTS characterization, with a proposed RTS detection methodology and counting. The designs presented exhibit a noteworthy decrease in the number of RTS occurrences, as evidenced by the experimental results.
Date of Conference: 14-18 April 2024
Date Added to IEEE Xplore: 16 May 2024
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Conference Location: Grapevine, TX, USA

References

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