In this paper cell and network level design of a mixed-mode cellular neural network is shown. First, second and third order polynomial feedback terms are included in the cell and Heun's integration method is used. In order to reduce the cell count, the array is designed so that it can process input data that has been divided into blocks. The whole input data is stored in parallel with the cells so that all input/output operations during processing are local. Cell structure is shown along with register connections between edge cells of the network. Analog power consumption and computing speed are estimated by HSPICE simulations using 0.25 /spl mu/m digital CMOS process parameters. The die area of a network with 2*72 cells with 36 layers in each is determined by drawing the layout.