Abstract:
A discrete time chaotic signal generator has been designed and fabricated in a 0.8 /spl mu/m single poly CMOS technology. The proposed chaotic circuit consists of sample-...Show MoreMetadata
Abstract:
A discrete time chaotic signal generator has been designed and fabricated in a 0.8 /spl mu/m single poly CMOS technology. The proposed chaotic circuit consists of sample-holds, opamps, a nonlinear function block and a two-phase clock generator. This paper examines numerical analysis for it's chaotic behavior including bifurcation, Lyapunov exponent and frequency spectra. Measurement of the fabricated chaotic chip is performed with a /spl plusmn/2.5 V power supply and clock frequency of 10 kHz. We confirmed that a discrete time chaotic signal is generated in specific input condition. Also, we obtained diverse chaotic behavior as expected from the numerical analysis.
Date of Conference: 26-29 May 2002
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-7448-7