This paper collects all the hardware constraints considered during the system-level design phase of the so-called DTCNN pixel-level snake algorithm (PLS-algorithm). These constraints, although focused on a particular algorithm, can be taken as general guidelines aimed to achieve the lowest coefficient circuit area in DTCNN. The validity of this approach is illustrated with some data about a 9/spl times/9 DTCNN PLS-algorithm chip, which nowadays is being made in the 0.25 /spl mu/m CMOS technology process provided by THOMSON.