A high-speed and low-power pipelined analog-to-digital converter was designed and simulated with a 0.18 /spl mu/m CMOS technology. Techniques of scaling down sampling capacitors and using low accuracy dynamic comparators are employed to reduce the power dissipation. Simulation results exhibit 10-bit operation at the sampling frequency of 100 MHz with SNDR of 60 dB, SFDR of 67 dB and THD of 63 dB at 2.34 MHz input. For 46.1 MHz input frequency, SNDR, SFDR and THD drop to 56 dB, 64 dB and 60 dB respectively. The estimated power dissipation from a single 1.8 V supply voltage is about 50 mW.