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Testability of path history memories with register-exchange architecture used in Viterbi-decoders | IEEE Conference Publication | IEEE Xplore

Testability of path history memories with register-exchange architecture used in Viterbi-decoders


Abstract:

Viterbi decoders with; register-exchange path-history contain a large number of registers and multiplexers. Insertion of scan-path registers for testing purposes would ge...Show More

Abstract:

Viterbi decoders with; register-exchange path-history contain a large number of registers and multiplexers. Insertion of scan-path registers for testing purposes would generate overhead in terms of area and power-consumption. To avoid scan-registers a, methodology is presented, that allows controlling the already available multiplexers in such a way, that the registers form non-merging chains that can be included in scan-paths.
Date of Conference: 26-29 May 2002
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-7448-7
Conference Location: Phoenix-Scottsdale, AZ, USA

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