In this paper, a new family of dynamic logic gates called Dual-rail Data-Driven Dynamic Logic (D/sup 4/L) is introduced. In this logic family, the synchronization clock signal has been eliminated and correct precharge and evaluation sequencing is maintained by appropriate use of data instances. The methodology and characteristics of D/sup 4/L are demonstrated in the design of a CLA 32-b adder and a 17-b high-speed multiplier. Based on VHDL simulations, the D/sup 4/L implemented 32-b adder has 23% less switching-activity than a comparable domino adder and for D/sup 4/L multiplier switching-activity is 14.5% less than its domino rival. HSPICE simulation in a 0.6 /spl mu/m CMOS process shows that D/sup 4/L has a 17% power saving over domino in a 32-b CLA adder design and a 10% saving in a 17-b multiplier design while a D/sup 4/L adder has 8% less delay than a domino one.