This paper presents two different FPGA-implementation of radix-4 butterflies suitable for HIPERLAN 2. The two approaches lead to an efficient use of the hardware resources available in the target device and reduces the area with respect to the direct implementation of the radix-4 butterfly. Both methods reduce the area required storing the coefficients. The first one uses the symmetries of coefficients for reducing the number of functions to store; the second one takes advantage of the dual-port capability of the embedded block-RAM.