This paper presents a dual-quantization cascade SC /spl Sigma//spl Delta/ modulator intended for A/D conversion in ADSL applications. The modulator combines a low oversampling ratio with 3-bit resolution in the last stage, to achieve 14bit@4.4MS/s (16/spl times/) and 15bit@2.2MS/s (32/spl times/) with no need of correction/calibration mechanisms. It consumes 66 mW from a single 2.5-V supply and has been implemented in 0.25-/spl mu/m CMOS technology.