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A micropower log domain FGMOS filter | IEEE Conference Publication | IEEE Xplore

A micropower log domain FGMOS filter


Abstract:

In this paper, a CMOS implementation of a low voltage micropower logarithmic biquad based on floating gate MOS transistors (FGMOS) is presented. The translinear principle...Show More

Abstract:

In this paper, a CMOS implementation of a low voltage micropower logarithmic biquad based on floating gate MOS transistors (FGMOS) is presented. The translinear principle applied to the floating gate MOS transistor leads to an easy implementation of the state-space equations without using the source terminal in the loop. The voltage supply can be reduced and also there is no need of separate wells. The technique is proven in this low/band pass filter working at 1 V with a maximum power consumption of 2 /spl mu/W. The filter parameters can be adjusted in more than two decades, being the upper frequency around 150 kHz.
Date of Conference: 26-29 May 2002
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-7448-7
Conference Location: Phoenix-Scottsdale, AZ, USA

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