This paper presents a physical synthesis methodology for ASIC datapath modules. It exploits the regularity information of datapath circuits and integrates the synthesis and placement processes together. This work is distinctive in the following aspects: (1) It works very well with datapath designs implemented in ASIC, where the datapath circuits are mostly semi-regular, therefore cannot be placed in a strict bit-sliced fashion. (2) It integrates physical planning with the synthesis process, so relative locations of the cells follow the bit order and the dataflow order. Experiments performed within a commercial framework show that this methodology improves the quality of datapath placements, and produces better post-route layouts for the datapath modules. This methodology narrows the performance gap between automatically generated ASIC datapath modules and manually constructed high-performance datapath circuits.