A new parallel architecture for the computation of a vector inner product is presented. The design is based on an extension of the radix-2/sup n/ design methodology previously proposed. In the new design, array multipliers without the final adder are used to produce the different partial product terms. This allows a more efficient use of 4:2-compressors and/or carry save adders for the accumulation of the products in the intermediate stages and reduces the numbers of accumulators by a factor of M, where M is the length of the vectors.