An efficient design for a high-speed, high-resolution parallel /spl Delta//spl Sigma/ architecture that is well suited to implementation in a digital CMOS process is presented here. The architecture uses a reduced sample-rate Leslie-Singh channel to enable sharing of one second stage ADC between the parallel channels. This results in reduced power consumption and smaller chip area. The design in this paper achieves 16 bits of resolution, with an 8 times oversampling ratio using a parallel system with four third-order channels and one 9-bit second stage.