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Memory exploration utilizing scheduling effects in high-level synthesis | IEEE Conference Publication | IEEE Xplore

Memory exploration utilizing scheduling effects in high-level synthesis


Abstract:

In this paper, we address one critical limitation of the previous work on the problem of memory exploration in high-level synthesis, namely, a tight coupling of schedulin...Show More

Abstract:

In this paper, we address one critical limitation of the previous work on the problem of memory exploration in high-level synthesis, namely, a tight coupling of scheduling effects with memory exploration, that has been ignored by most existing memory synthesis systems. To overcome the limitation, we propose an integrated approach that takes into account the memory configurations and schedules simultaneously. Experimental data on a set of benchmark filter designs are provided to show the effectiveness of the proposed exploration strategy in finding close-to-optimal memory configurations.
Date of Conference: 26-29 May 2002
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-7448-7
Conference Location: Phoenix-Scottsdale, AZ, USA

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