Loading [a11y]/accessibility-menu.js
Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions | IEEE Conference Publication | IEEE Xplore

Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions


Abstract:

This contribution presents a VHDL-AMS model for a building block present in a multi-channel neural network based on the adaptive resonance theory, and its automated synth...Show More

Abstract:

This contribution presents a VHDL-AMS model for a building block present in a multi-channel neural network based on the adaptive resonance theory, and its automated synthesis using a VHDL-AMS to HSPICE netlist translator. This building block shows continuous dynamic behavior, and it is complex enough to check the functionality of our translator. Both simulations, the behavioral high-level one based on the VHDL-AMS model and the structural one based on an automatically synthesized SPICE description, have verified the matching between the SPICE netlist synthesized against its VHDL-AMS model.
Date of Conference: 26-29 May 2002
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-7448-7
Conference Location: Phoenix-Scottsdale, AZ, USA

Contact IEEE to Subscribe

References

References is not available for this document.