In this paper we propose an interconnection scheme for the autonomous error-tolerant (AET) cell introduced in a paper by Valtonen et al. (2001). The objective here is to partition the system into identical, physically autonomous and highly configurable cells that can operate without outside control or synchronization. In billion transistor Network-on-Chip (NoC) circuits, an AET cell fabric could prove highly flexible and reliable, and allow for low replication costs, due to homogeneousity. However, many challenges persist before a useful system can be constructed: the need for (i) scalable long-distance communication-global bus wiring fits poorly into a homogeneous, symmetric fabric and limits scalability, (ii) flexible communication-cells in all directions, within a given range, should be accessible and (iii) self-synchronizing topologies, due to the absence of external synchronization; (iv) the interconnect scheme is to be implemented using near-future technology generations, and (v) the fabric should be efficient when constituting billions of cells.