Tree-structured mismatch-shaping DACs have recently been used as enabling components in state-of-the-art /spl Delta//spl Sigma/ ADCs to suppress signal-band error arising from mismatches among fabricated DAC components. This paper presents a segmented version of the encoder with significantly reduced hardware complexity. The segmented architecture follows from a result that any digital encoder for which the output values sum to the input value can be implemented using a tree-structured encoder.