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Compact continuous-time analog rank-order filter implementation in CMOS technology | IEEE Conference Publication | IEEE Xplore

Compact continuous-time analog rank-order filter implementation in CMOS technology


Abstract:

A simple CMOS implementation of a continuous-time analog rank-order N input filter is presented that uses N operational transconductance amplifiers. Rank is digitally pro...Show More

Abstract:

A simple CMOS implementation of a continuous-time analog rank-order N input filter is presented that uses N operational transconductance amplifiers. Rank is digitally programmable for all values from k=1 (min case) to k=n (max case). The implementation is based on a compact transconductor with high transconductance gain and symmetrical output current saturating characteristics. Experimental and simulation results are presented that verify functionality and the high frequency characteristics of the proposed implementation.
Date of Conference: 26-29 May 2002
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-7448-7
Conference Location: Phoenix-Scottsdale, AZ, USA

1. INTRODUCTION

A rank order filter (ROF) is a generalization of several common nonlinear and linear filtering operations which include the min, max, median and average operators among others [1] – [11]. High-speed analog ROFs can find applications in various fields such as real-time nonlinear image processing, speech processing, data compression, communications, neural and fuzzy networks, etc. In an ROF filter with N input signals, the k-th rank order signal is defined as the k-th signal in increasing order of amplitude. For an N-input ROF, the min case corresponds to , the max case to and the median case to . Three basic approaches have been proposed for the analog implementation of ROFs: a) feedforward systems based on multistage sorting min and max circuits that order signals in increasing order of magnitude [6] – [8]. In this approach, the number of stages increases with the number of input signals N b) Continuous-time negative feedback approaches based on high gain transconductors with symmetrical output current saturation characteristics [9]. This approach provides the kth rank order signal in just one step and c) Sample data approaches based on capacitive threshold logic [10] – [11]. The hardware complexity of this approach grows rapidly with N and it has an inherent speed limitation due to sample data operation. Two stage transconductance amplifier: (a) Internal structure. (b) Symbol (c) DC Transconductance characteristic.

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References

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