Abstract:
This paper describes a Self-Timed MOS Current-Mode Logic (ST-MCML) for digital applications. The architecture and operation of ST-MCML is explained and analyzed. 4-bit ri...Show MoreMetadata
Abstract:
This paper describes a Self-Timed MOS Current-Mode Logic (ST-MCML) for digital applications. The architecture and operation of ST-MCML is explained and analyzed. 4-bit ripple and 16-bit carry look ahead adders are implemented using the ST-MCML technique in a 0.18-/spl mu/m, 1.8-V, 1-GHz CMOS process. ST-MCML is compared to conventional MCML, static CMOS and domino logic in terms of power, delay, Power-Delay-Product (PDP) and Energy-Delay-Product (EDP). ST-MCML achieves low-power values as well as minimum PDP and EDP values.
Published in: 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)
Date of Conference: 26-29 May 2002
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-7448-7
Contents 