We propose a novel bit plane error resilient entropy coding scheme for DCT-based image compression, which can control and minimize the error propagation effect. The compressed rate is similar to the JPEG standard. However, it uses only 18 VLC symbols. Hardware implementation cost and power consumption can then be minimized. Base on simulation results, the proposed coding scheme can achieve high image quality (PSNR=29.82 dB) even at bit error rate of 10/sup -3/. An image codec has been implemented for verifying the proposed bit-plane EREC coding technique. It can compress and decompress CIF size (352/spl times/288, 4:2:0 format) images at the rate of 30 frames per second using 20 MHz clock rate. It only occupies 36 k gate count and 1.90/spl times/1.90 mm/sup 2/ silicon area in a 0.35 /spl mu/m CMOS process. With 3.3 V power supply, the simulated power consumption is only 27 mWatt and 0.41 mA/MHz. This performance can meet various wireless portable multimedia system requirements.