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Charge-based MOS correlated double sampling comparator and folding circuit | IEEE Conference Publication | IEEE Xplore

Charge-based MOS correlated double sampling comparator and folding circuit


Abstract:

A novel charge-based comparator and folding circuit are presented. Correlated double sampling comparison is performed using a log-domain integrator, implemented by a subt...Show More

Abstract:

A novel charge-based comparator and folding circuit are presented. Correlated double sampling comparison is performed using a log-domain integrator, implemented by a subthreshold nMOS transistor with the source coupled to a capacitor. The circuit produces a current that is a logistic function of the change in voltage on the gate, with an input-referred offset voltage that is a logarithmic function of time. Folding operation for analog-to-digital conversion is obtained by differentially combining currents from a bank of these comparators. A prototype 128-channel parallel 4-bit gray-code analog-to-digital converter has been implemented in a 0.5 /spl mu/m CMOS process, delivering 128 MS/sec at 76 mW power dissipation.
Date of Conference: 26-29 May 2002
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-7448-7
Conference Location: Phoenix-Scottsdale, AZ, USA

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