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On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process | IEEE Conference Publication | IEEE Xplore

On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process


Abstract:

A novel design concept to turn on the SCR device by applying the substrate-triggered method is first proposed in the literature for effective on-chip ESD protection desig...Show More

Abstract:

A novel design concept to turn on the SCR device by applying the substrate-triggered method is first proposed in the literature for effective on-chip ESD protection design. To avoid the transient-induced latch-up issue, the substrate-triggered SCR devices are stacked in the ESD protection circuits. The turn-on efficiency of the SCR can be greatly improved by applying the substrate-triggered method. The on-chip ESD protection circuits designed with the substrate-triggered SCR devices for input pad, output pad, and power pad have been successfully verified in a 0.25 /spl mu/m CMOS process. The substrate-triggered SCR device with a smaller layout area of only 40 /spl mu/m/spl times/20 /spl mu/m can sustain an HBM (human-body-model) ESD stress of higher than 7 kV.
Date of Conference: 26-29 May 2002
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-7448-7
Conference Location: Phoenix-Scottsdale, AZ, USA

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