A new effective silicon implementation of a Reed Solomon engine is presented. By a further optimization of the modified Berlekamp Massey algorithm presented by Jeng and Troung (1999), the number of Galois Field (GF) multipliers involved in the calculation of the errata locator polynomial can be shown to be a linear function of the number of parity symbols. The use of a circular structure in the calculation of the discrepancy makes the calculation itself independent of the number of iterations involved in the algorithm. New variables are introduced in the error magnitude calculation in order to use hardware resources already present, thus minimizing the number of logic gates. Along with the codeword length and the number of parity bytes, programmability involves GF primitive polynomials and the code generator polynomial. Results in terms of gate count, throughput and latency show a competitive advantage when compared to existing Reed Solomon engines, as well as allowing a wider programmability.