An area-efficient systolic division circuit over GF(2/sup m/) for secure communication | IEEE Conference Publication | IEEE Xplore

An area-efficient systolic division circuit over GF(2/sup m/) for secure communication


Abstract:

We present a novel area-efficient parallel-in parallel-out systolic division circuit (v = a/b) over GF(2/sup m/) based on the extended Stein's algorithm. By keeping the c...Show More

Abstract:

We present a novel area-efficient parallel-in parallel-out systolic division circuit (v = a/b) over GF(2/sup m/) based on the extended Stein's algorithm. By keeping the combined area-time (AT) complexity at the lowest level of O(m/sup 2/), we evenly distribute the complexity of O(m) in area and time, and design a well-balanced division circuit capable of operating at high speed with high area efficiency. Compared to the other systolic architectures, our design exhibits significant advantages in both area and time.
Date of Conference: 26-29 May 2002
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-7448-7
Conference Location: Phoenix-Scottsdale, AZ, USA

Contact IEEE to Subscribe

References

References is not available for this document.