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A high-resolution and fast-conversion time-to-digital converter | IEEE Conference Publication | IEEE Xplore

A high-resolution and fast-conversion time-to-digital converter


Abstract:

This paper describes a design of time-to-digital converter (TDC), which has the features of high-resolution and fast conversion. With the aid of the gate delay difference...Show More

Abstract:

This paper describes a design of time-to-digital converter (TDC), which has the features of high-resolution and fast conversion. With the aid of the gate delay difference technique, the TDC can achieve a sub-gate delay resolution. The flash-type operation enables the TDC to resolve the time difference for fine conversion in less than one reference clock cycle. The differential non-linearity (DNL) can be less than /spl plusmn/0.03 LSB and integral non-linearity (INL) less than /spl plusmn/0.04 LSB. We confirm the results based on 0.35 /spl mu/m CMOS process technology.
Date of Conference: 25-28 May 2003
Date Added to IEEE Xplore: 20 June 2003
Print ISBN:0-7803-7761-3
Conference Location: Bangkok, Thailand

References

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