Loading [a11y]/accessibility-menu.js
Analysis of phase noise due to bang-bang phase detector in PLL-based clock and data recovery circuits | IEEE Conference Publication | IEEE Xplore

Analysis of phase noise due to bang-bang phase detector in PLL-based clock and data recovery circuits


Abstract:

This paper describes the noise analysis of phase-locked loop (PLL) based clock and data recovery circuits (CDR) using bang-bang phase detectors (PD). The analysis is base...Show More

Abstract:

This paper describes the noise analysis of phase-locked loop (PLL) based clock and data recovery circuits (CDR) using bang-bang phase detectors (PD). The analysis is based on modeling the non-linearity of the bang-bang PD with a linear PD and an additive white noise source. This analysis shows that the input PD noise and the PLL DC gain are both proportional to the quantization step of the PD determined by the amplitude of the charge-pump current. To reduce the input PD noise without degrading the PLL DC gain and the loop bandwidth, a multilevel PD can be used instead. The theoretical results predict tendencies that agree with circuit simulations.
Date of Conference: 25-28 May 2003
Date Added to IEEE Xplore: 20 June 2003
Print ISBN:0-7803-7761-3
Conference Location: Bangkok, Thailand

References

References is not available for this document.