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Bonding-pad-oriented on-chip ESD protection structures for ICs | IEEE Conference Publication | IEEE Xplore

Bonding-pad-oriented on-chip ESD protection structures for ICs


Abstract:

Several bonding-pad-oriented ESD protection structures, including a ggCMOS, an LVSCR and an all-direction ESD structures are reported, implemented in commercial 0.35 /spl...Show More

Abstract:

Several bonding-pad-oriented ESD protection structures, including a ggCMOS, an LVSCR and an all-direction ESD structures are reported, implemented in commercial 0.35 /spl mu/m CMOS and 0.6 /spl mu/m BiCMOS. Measurements agree with simulations well. HBM ESD zapping tests passed 2 kV, 4.4 kV and 14 kV, respectively. The structures are suitable ESD protection solutions for RF, mixed-signal and high-pin-count ICs.
Date of Conference: 25-28 May 2003
Date Added to IEEE Xplore: 20 June 2003
Print ISBN:0-7803-7761-3
Conference Location: Bangkok, Thailand

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