The design of a 10.7-MHz 4/sup th/-order fs/4 bandpass sigma-delta modulator with a double-delay single-opamp resonator plus double-sampling technique is proposed for GSM standard. The circuit is implemented in 0.35-/spl mu/m double-poly, triple-metal CMOS process. Both behavioral-level and transistor-level simulation results are presented, and the circuit is expected to achieve >80 dB dynamic range, occupying 0.15 mm/sup 2/ active area and less than 12mW power consumption at 2.5V supply.