Most of the scheduling schemes proposed in the literature require complex calculations per flow and thus, their implementations are expensive, especially in terms of silicon area. Additionally, when these algorithms work at gigabit rates, they cannot support large numbers of network flows each with diverse rate requirements. Although nowadays it is technologically viable to implement such mechanisms that can provide QoS in hardware, this can be accomplished only if lower rates (couple of hundreds Mbits/sec at most) or small number of flows (few hundreds) are serviced by the scheduling mechanism. This paper introduces a novel scheduling scheme which can handle thousands of traffic flows, each with its own QoS parameters, at an aggregate rate of 10 Gbps. The hardware implementation of this algorithm requires only 17500 standard CMOS gates. This novel scheme is also very flexible and thus it can very easily be integrated in a large number of different high-performance networking Systems-on-Chip (SoCs).