In the wireless mobile communication system, a decision feedback equalizer (DFE) to cancel the inter symbol interference (ISI) is required. This paper analyzes and implements the decision feedback equalizer and a novel CCK architecture of the receiver. All the filters are implemented using the finite impulse response (FIR) filter. The least mean square (LMS) algorithm with initial values is used for updating the coefficient as fast as it can be in the parallel DFE architecture. The area requirement of the novel CCK demodulator structure is about half of that of Fast Walsh Block structure, while their delay times are approximately the same. After synthesis, the total gate counts of the DFE and the CCK demodulator are 58624 and 9937, respectively. The power consumption of DFE is 25.087 mW operating under a 3.3 V supply voltage.