For VLSI systems the parallel bus interface using the CDMA technique is proposed, which has low power consumption and high noise tolerance. The proposed interface can transfer data between a transmitter and a receiver in one clock. It has tolerance to the timing variation in the signal transfer among every buses which is an advantage compared with conventional parallel bus. The 15 bit parallel CDMA bus interface with the access speed of 2.5 Gb/s had been successfully implemented with 0.35 /spl mu/m CMOS technology.