This paper presents a Field Programmable Gate Array (FPGA) implementation for video compression using a Block Truncation Coding (BTC) image compression technique. The implementation exploits the inherent parallelism of the BTC algorithm to provide efficient algorithm-to-architecture mapping. The Xilinx VirtexE BTC implementation has shown to provide 20.5 /spl times/ 10/sup 6/ of pixels per second, which is about 3000 times faster than an Intel Pentium III 550 MHz processor.