A cost-effective hardware architecture of integer, half, and quarter-pel motion estimation for MPEG-4 Advanced Simple Profile is proposed in this paper. Three-step hierarchy scheme is employed to cope with different pixel accuracy. For integer-pel estimation, the proposed computation-controllable algorithm makes it easy to be integrated into the coding system according to the power, quality, and timing conditions. For half and quarter-pel motion estimation, hardware-oriented algorithm and related architecture are proposed for cost reduction and provide 1.63 to 4.81 dB improvement in PSNR quality. The implementation takes 15K gates at 54MHz for sequences of CIF format at 30 fps.