The goal of the research is twofold: first, the derivation of a design methodology for FIR filter implementation based on the Residue Number System (RNS), aiming at power, delay and hardware complexity reduction compared with conventional binary implementations. Second, a CAD tool development, which generates a synthesizable VHDL description of any RNS system design in an automatic way. This tool can derive RNS full adder-based DSP architectures consisting of FIR, scaling, converters, multiplication and accumulation units.