A systematic methodology for generating software-based self-tests for microprocessor cores is introduced in this paper. The produced software tests emulate the functionality of a scan path design, and can be applied during the normal-operation mode of the microprocessor, thus enabling at-speed testing. A major advantage of the proposed approach lies in the fact that the generation of the software tests does not require any knowledge about the low-level implementation of the microprocessor and is only based on its RT-level description and its instruction set architecture.