This paper describes novel flip-flops for achieving improved robustness and low power consumption. Variable sampling window flip-flop (VSWFF) improves robustness during latching operation by varying the width of the sampling window according to input data. It also reduces overall power consumption for higher input switching activities, and provides shorter hold time and better input noise rejection. Clock swing-reduced variable sampling window flip-flop (CSR-VSWFF) further reduces the power consumption by allowing use of a small swing clock. As compared to conventional reduced clock swing flip-flops, CRS-VSWFF requires no extra high power supply voltage. The simulation results indicate that VSWFF significantly improves robustness during latching operation with 10% reduction on the maximum power consumption, while CSR-VSWFF improves the power-delay product by about 64% as compared to the conventional flip-flops.