An ultra-low-power DSP decimation/interpolation structure is described demonstrating how algorithmic and architectural schemes were employed for ultimate power efficiency in a DSP based chip set for audio applications. This circuit was designed and synthesised for a low V/sub T/ 0.35 /spl mu/m CMOS process allowing Nyquist rate signals to be decimated from a high OSR /spl Sigma/-/spl Delta/ front-end and interpolation post voice processing at the back end. The DSP has been fabricated and operates down to 0.9 V. At 1.25 V, its current consumption is only 90 /spl mu/A.