Abstract:
Many new dynamic logic family techniques require a chain of delayed clocks separated by a time that is usually less than a buffer delay. This paper presents a technique t...Show MoreMetadata
Abstract:
Many new dynamic logic family techniques require a chain of delayed clocks separated by a time that is usually less than a buffer delay. This paper presents a technique to generate these clocks and distribute them to the logic gates. The system has tuning abilities so that even with process-voltage-temperature (PVT) variation in the distribution paths, it can correct itself. Extraction results for a 0.18um process showed +/- 3ps deviation from a nominal 50ps clock separation for a chain of 10 clocks at 1GHz.
Published in: Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.
Date of Conference: 25-28 May 2003
Date Added to IEEE Xplore: 20 June 2003
Print ISBN:0-7803-7761-3